1. Field of the Invention
This invention relates to a semiconductor circuit device such as memory, photoelectric converting device, signal processing device, etc. to be mounted on various electronic instruments, particularly to a metal wiring structure and a semiconductor device improved in device separation structure.
2. Related Background Art
Conventionally, device separation in semiconductor device has been constituted as shown in FIG. 1A. In FIG. 1A, the symbol 1 is metal wiring, 2, 3 are device regions where transistor, FET, resistance, condenser, photosensor, etc. are formed, and electrical insulation thereof is effected by the device separation region, namely the Si substrate 4 doped with an impurity or the Si layer 5 doped with the same impurity. The potentials of the device separation regions of 4, 5 are fixed by the metal wiring 1 or 6.
For example, the device separation region of a solid image pick-up device is constituted as shown in FIG. 1B. In the Figure, the symbol 4 is a P type substrate, 5' an n.sup.+ buried layer, 2 an n.sup.- epitaxial growth layer (hereinafter epitaxial growth is written as epi), 5 an n.sup.+ layer. The above n.sup.- epi layer 2 is a photoelectric converting region, and the n.sup.+ buried layer 5' and the n.sup.+ layer 5 are device regions.
The n.sup.- epi layer 2 is maintained at a certain positive potential through the n.sup.+ buried layer 5' and the n.sup.+ layer 5. By the build-in electrical field through junction between the n.sup.- epi layer 2 and the n.sup.+ layer 5, the electrons formed by photoirradiation are absorbed in the n.sup.+ buried layer 5 and the n.sup.+ layer 7, and the positive holes cannot be diffused to the confined adjacent picture elements, whereby cross-talk can be prevented.
However, prior art examples had the technical tasks as follows.
(1) There was an impedance of about some ten to some hundred .OMEGA./.quadrature.. For this reason, current flowed into the region 5, and when the potential is elevated, parasitic transistor turned on between the device regions 2 and 3, whereby latch-up or unstable actuation of function was caused to occur.
(2) On account of the impedance in the region 5, cross-talk in the device regions 2 and 3 was generated to cause unstable actuation.
Particularly in the case of a solid image pick-up device,
(3) The positive holes having acquired thermally high energy will be diffused to the adjacent picture elements.
(4) Since the device separation region is also a semiconductor, carriers will be generated when light is irradiated.
(5) The width of the n.sup.+ -Si device separation cannot be made narrow in process to obstruct reduction of picture element, whereby higher resolving power of solid image pick-up device has been obstructed.
On the other hand, as the metal wiring structure in a highly integrated semiconductor device, for example, there has been known one having an interlayer insulating film 52 comprising silicon oxide, etc. formed on the surface of a semiconductor substrate 51 comprising silicon and a metal wiring layer 53 comprising Al, Al--Si, etc. formed on the interlayer insulating film 52 as shown in FIG. 2A.
In the semiconductor device equipped with the metal wiring of such structure, the sectional area of wiring has been increased by enlargement of the width dimensions of the respective wirings, thereby ensuring necessary current tolerant capacities for the respective wirings, and therefore the flat area of wiring will be increased and improvement of wiring without increasing the device size is limited.
For this reason, for improvement of wiring density, for example, a semiconductor device of a wiring structure having the respective wirings laminated in multiple layers as shown in FIG. 2B has been known.
In this semiconductor device, two layers of metal wiring are laminated through an insulating film.
In the following, the outline of the process for preparing the semiconductor device shown in 2B is described.
First, after formation of various necessary functional devices such as bipolar transistor, MOS transistor, MOS diode, etc. on a part of the surface of the semiconductor substrate 1, on the remaining surface of the semiconductor substrate 51 is formed a first interlayer insulating film 52 comprising PSG (Phospho silicate glass), etc. according to the normal pressure CVD method with a thickness of 0.5 to 1.0 .mu.m, and the first interlayer insulating film 52 is applied with annealing.
Next, patterning by use of a resist is applied on the first interlayer insulating film 52 as described above to form openings 52a for taking out electrodes of various functional devices. Subsequently, according to the sputtering method, after deposition of a wiring material comprising, for example, Al--Si according to the sputtering method on the surface of the first interlayer insulating film 52 and internally of the openings 52a, the first wiring layer 53 is formed by patterning by use of a resist.
Next, on the first wiring layer 53 and the first interlayer insulating film 52 are formed a second interlayer insulating film 54 comprising PSG with a thickness of about 0.5 to 1.0 .mu.m according to the normal pressure CVD method, openings 54a for connecting the first wiring layer and the upper wiring layer as described below to a part of the second interlayer insulating film 54 corresponding to the upper portion of the first wiring layer 53 are formed.
Next, on the second insulating film 54 and internally of the openings 54a, a wiring comprising, for example, Al--Si is deposited, followed by formation of the second wiring layer 55 for connecting the second wiring layer 55 for connecting the first wiring layer 53 through the portion of the openings 54a by patterning.
Next, on the second interlayer insulating film 54 and the second wiring layer 55, a passivation film 6 can be formed with a thickness of 0.5 to 1.0 .mu.m according to the plasma CVD method to prepare a semiconductor device with a metal double layer wiring structure shown in FIG. 2B.
In the semiconductor device having a multi-layer wiring structure of such constitution, a wiring with wiring density by far higher than the semiconductor device with the monolayer wiring structure shown 2A can be realized.
However, in the semiconductor device having a multi-layer wiring structure as described above, since an interlayer insulating film is provided between the wiring at the lower part and the wiring at the upper part, the surface stepped difference due to the wiring portion will become greater as the number of the lamination increases, whereby the degree of freedom in design in the wiring structure is regulated because of movement of the position (migration) of the wiring portion relative to the semiconductor substrate at the wiring portion or the shape of the contact hole necessary for connection between the respective insulating layers. Thus, also in this case, improvement of wiring density is limited and it has been difficult to enhance wiring density more than a certain level.
Further, in a semiconductor device with a multi-layer structure, surface unevenness becomes greater as the layer is upper, and therefore slippage in alignment becomes greater during mask registration in patterning when laminating further wiring, whereby wiring could not be formed with good precision at the predetermined position relative to the semiconductor substrate, thus involving the problem with respect to reliability of wiring.